NCP1605DR2G【PDF 20/32 页】IC PFC CONTROLLER CCM/DCM 16SOIC

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Sheet目录45

16页 17页 18页 19页 [20页]21页 22页 23页 24页

NCP1605, NCP1605A, NCP1605B

http://onsemi.com

0,00

50,00

100,00

150,00

200,00

250,00

300,00

350,00

time (ms)

0,00

0,50

1,00

1,50

2,00

2,50

3,00

3,50

Figure 57. Input Voltage and Ontime vs Time (example with F

= 100 kHz, Pin =150 W, V

= 230 V, L = 200 mH)

Regulation Block and Low Output Voltage Detection

A transconductance error amplifier with access to the

inverting input and output is provided. It features a typical

transconductance gain of 200 mS and a maximum

capability of ?0 mA. The output voltage of the PFC stage

is typically scaled down by a resistors divider and

monitored by the inverting input (feedback pin Pin 4).

The bias current is minimized (less than 500 nA) to allow

the use of a high impedance feedback network. The output

of the error amplifier is pinned out for external loop

compensation (Pin 3). Typically a capacitor in the range of

100 nF, is applied between Pin 3 and ground, to set the

regulation bandwidth below 20 Hz, as need in PFC

applications.

The swing of the error amplifier output is limited within

an accurate range:

" It is forced above a voltage drop (V

) by some circuitry.

" It is clamped not to exceed 3.0 V + the same V

voltage

drop.

Hence, V

Pin3

features a 3 V voltage swing. V

Pin3

is then

offset down by (V

) and divided by three before it connects

to the V

TON

processing block and the PWM section.

Finally, the output of the regulation is a signal (V

REGUL

of the block diagram) that varies between 0 and 1 V.

ref

Figure 58. Regulation Block

OFF

?0 mA

OVLflag1

3 V

0.955*Vref

pfcOK

200 mA

Figure 59. Correspondence between V

CONTROL

and V

REGUL

1 V

0 V

REGUL

CONTROL

3 V + V

control

out

Low

Detect

Error

Amplifier

REGUL

Provided the low bandwidth of the regulation loop, sharp

variations of the load, may result in excessive over and

undershoots. Overshoots are limited by the Overvoltage

Protection (see OVP section). To contain the undershoots, an

internal comparator monitors the feedback (V

Pin4

) and when

Pin4

is lower than 95.5% of its nominal value, it connects a

200 mA current source to speedup the charge of the

compensation capacitor (Cpin3). Finally, it is like if the

comparator multiplied the error amplifier gain by 10.

One must note that this circuitry for undershoots limitation,

is not enabled during the startup sequence of the PFC stage

but only once the converter has stabilized (that is when the

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